1. Field of the Invention
The present invention relates to a scanning circuit composed of plural stages of unit circuits for releasing scanning pulses of two or more phases in succession according to multi-phase driving pulses.
2. Related Background Art
FIG. 1 is a schematic circuit diagram of a conventional scanning circuit.
The conventional example is composed of n stages of units circuits, which release scanning pulses .phi.11, .phi.21, .phi.12, . . . in succession.
In the unit circuit of the first stage, and in the presence of a start pulse .phi.hs, a transistor M1 is rendered conductive by a pulse .phi.h2 to elevate a potential V(1). A transistor M2 shows a conductance corresponding to the potential V(1) which is the gate potential of the transistor M2.
Then, the pulse .phi.h2 is terminated and a pulse .phi.h1 is started, the potential of a terminal Op1 starts to rise through the transistor M2. The potential rise is fed back to the gate of the transistor M2 through a capacitor C1, thereby elevating the potential V(1). As the rise of the potential V(1) increases the conductance of the transistor M2, the terminal OP1 provides a scanning pulse .phi.11 without voltage drop.
Also the first pulse .phi.11 elevates the potential V(2) of a second stage through a transistor M3. Thus, at the upshift of the pulse .phi.h2, a terminal OP2 outputs a scanning pulse .phi.21 through a transistor M6.
At the same time, the pulse .phi.h2 turns on the transistor M1, thereby reducing the potential V(l) to a reference potential. Also a scanning pulse .phi.12 of a third stage turns on a transistor M5, thereby reducing the potential V(2) to the reference potential.
In this manner the scanning pulses are generated in succession according to the timing of the pulses .phi.ha and .phi.h2.
FIG. 2A is a circuit diagram showing an example of a signal reading device utilizing a conventional scanning circuit, and FIG. 2B is a timing chart showing an example of the function thereof.
In the initial state it is assumed that in capacitors Ct.sub.1 and Ct.sub.2 a sensor noise N and a sensor signal S containing noise are respectively accumulated.
At the application of a high-level scanning pulse .phi.11 with a pulse duration Tb, transistors Qt1 and Qs1 are turned on, whereby the sensor noise N stored in the capacitor Ct1 is released to an output line OUT1 through a bipolar transistor amplifier Q.
After the noise N is read for a duration Tc (&lt;Tb), a pulse .phi.bc is shifted to the high level while the scanning pulse .phi.11 remains at the high level to turn on a transistor Qbc, thereby resetting the capacitor Ct1 and the base of a transistor Q.
Then, by a scanning pulse .phi.21 and a pulse .phi.bc, the sensor signal S stored in the capacitor Ct2 is released to an output line OUT2 for a duration Tc in a similar manner to the readout the Capacitor Ct.sub.1.
The noise N and the sensor signal S supplied respectively to the output lines OUT1, OUT2 are subjected to a subtraction process, thereby eliminating the noise from the sensor signal S.
At the same time the output of the bipolar transistor Q is supplied to the output line OUT1 or OUT2 through the turn-on resistance of a transistor Qs1 or Qs2, thereby suppressing the feed-back through a diffusion capacitor and thus reducing the noise component.
However, in such conventional structure, the effective period of reading the signal stored in the capacitors Ct1, Ct2 is Tc, which, as shown in FIG. 2B, is very short after the subtraction of the resetting period for the remaining component, in the duration Tb of the scanning pulse.
For this reason the signal reading device utilizing the conventional scanning circuit is unable to provide a sufficiently high S/N ratio, thus being unable to achieve a high sensitivity when applied to an imaging sensor.
Also in the conventional scanning circuit, since with the feedback resetting structure in which each stage is reset by the output scanning pulse of a succeeding stage, there is required an additional circuit exclusively for resetting the last stage, and the simultaneous resetting of all the stages prior to the start of the scanning circuit is not possible.
In order to eliminate such drawbacks there has been proposed a structure of connecting resetting transistors respectively to the gate electrodes of the transistors M2 and giving a resetting pulse commonly to the gate electrodes of said resetting transistors, but the connection of another transistor to the gate electrode of the transistor M2 increases the parasite capacity thereof, thereby reducing the boot strap effect.
Also it is possible to activate the resetting transistor M4 of each stage by another pulse, instead of the scanning pulse from the succeeding stage, but the scanning circuit becomes inevitably complex for generating such another pulse.